In simple terms
A friendly intro before the formal notes — no formulas yet.
The CPU's Grand Plan
The CPU is the 'brain' of the computer, constantly running a simple, three-step dance to process instructions. It fetches an instruction from memory, decodes it to understand what to do, and then executes it.
Imagine a master chef (the CPU) working in a kitchen. The recipe book is main memory (RAM), containing both the cooking steps (instructions) and the list of ingredients (data). The chef fetches one step from the book, reads it, gathers the required ingredients from a small, super-fast spice rack on the counter (the registers), performs the action (like chopping or mixing), and then moves on to the next step in the recipe. This fetch-decode-execute process repeats until the dish is complete.
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First, the CPU 'fetches' the next instruction from main memory, using a special pointer called the Program Counter to know where to look.
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Next, the Control Unit 'decodes' the instruction, breaking it down to understand the operation required and what data is needed.
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Then, the CPU 'executes' the command. This could be a calculation by the Arithmetic Logic Unit or moving data between memory and registers.
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Finally, the result is stored, and the Program Counter is updated to point to the next instruction, starting the cycle all over again.
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Full topic notes
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The Von Neumann Architecture
Most modern general-purpose computers are based on the Von Neumann architecture. This design is defined by the stored program concept, which is the idea that not only data but also the program instructions are stored together in the same main memory. This was a revolutionary concept, as early computers had programs hard-wired into their circuitry. With the stored program concept, a computer could be reprogrammed simply by loading a new program into its memory.
Instructions and data are stored in the same memory unit.
Instructions and data use the same bus to travel between the memory and the CPU.
Instructions are fetched and executed sequentially, one after another.
This design allows a program to be treated as data, meaning it can be read, modified, and written just like any other data.
Core Components of the CPU
A CPU contains several key components that work together to process instructions. The three main parts are the Control Unit (CU), the Arithmetic and Logic Unit (ALU), and the Registers.
Control Unit (CU): This is the director of operations. It fetches instructions from memory, decodes them, and sends out control signals to coordinate the other parts of the CPU and computer to execute the instruction.
Arithmetic and Logic Unit (ALU): This is the calculator of the CPU. It performs all arithmetic operations (like addition and subtraction) and logical comparisons (like AND, OR, and NOT).
Registers: These are small, high-speed storage locations within the CPU. They hold data, instructions, and addresses that are needed for immediate processing, providing much faster access than main memory (RAM).
Special-Purpose Registers
While a CPU has several general-purpose registers, some are dedicated to specific, crucial roles in the Fetch-Decode-Execute cycle. You must know the name and function of each.
Program Counter (PC): Holds the memory address of the next instruction to be fetched.
Memory Address Register (MAR): Holds the memory address of the instruction or data that is about to be fetched or stored.
Memory Data Register (MDR): Temporarily holds the data or instruction that has just been fetched from memory or is about to be written to memory. It's the gateway between the CPU and the data bus.
Current Instruction Register (CIR): Holds the current instruction being decoded and executed.
Accumulator (ACC): A register used to store the results of calculations performed by the ALU.
The Fetch-Decode-Execute Cycle
The primary job of the CPU is to continuously perform the Fetch-Decode-Execute (FDE) cycle. This is the sequence of steps taken to process a single machine code instruction. The cycle is managed by the Control Unit and synchronised by the system clock.
- Fetch: Get the instruction from memory.
- Decode: Understand what the instruction means.
- Execute: Carry out the instruction.
The System Bus
The CPU, main memory, and other components are connected by a set of parallel wires called the system bus. It is comprised of three separate buses, each with a specific function. The width of these buses (the number of parallel wires) can impact system performance.
Address Bus: A unidirectional bus that carries memory addresses from the CPU to main memory and other I/O devices. The width of the address bus determines the maximum amount of memory the CPU can address (e.g., a 32-bit address bus can address unique locations).
Data Bus: A bidirectional bus that carries the actual data and instructions between the CPU, memory, and I/O devices. Its width affects how much data can be transferred in a single cycle.
Control Bus: A bidirectional bus that transmits command, timing, and status signals between system components. For example, it carries the 'memory read' and 'memory write' signals, clock pulses, and interrupt requests.
Factors Affecting CPU Performance
The speed of a CPU is not determined by a single factor. Several characteristics of its design and the surrounding system architecture contribute to its overall performance.
Clock Speed: Measured in Gigahertz (GHz), this is the number of FDE cycles the CPU can theoretically perform per second. A 3 GHz CPU performs 3 billion cycles per second. While a higher clock speed generally means faster performance, some instructions may take more than one clock cycle to complete.
Number of Cores: A core is an independent processing unit within the CPU. A multi-core CPU (e.g., dual-core, quad-core) can execute multiple instructions simultaneously, provided the software is designed for parallel processing. This is highly effective for multitasking or running complex applications like video editing.
Cache Memory: A small amount of very fast, expensive static RAM (SRAM) built into the CPU or placed very close to it. It stores frequently accessed data and instructions, saving the CPU from having to fetch them from the much slower main memory (DRAM). More cache (and faster cache, e.g. L1 vs L2) significantly reduces processing bottlenecks.
Worked examples
See the formulas applied — reveal one step at a time, like the exam.
An instruction ADD #5 is stored at memory location 102. The Program Counter (PC) currently holds 102 and the Accumulator (ACC) holds the value 12. Describe the steps of the Fetch-Decode-Execute cycle for this instruction, showing the state of the PC, MAR, MDR, CIR, and ACC.
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The instruction means 'add the immediate value 5 to the contents of the Accumulator'.
An instruction LDA 250 is being executed. This instruction means 'load the data from memory address 250 into the Accumulator'. The data at address 250 is the value 99. Describe the 'Execute' phase of the FDE cycle for this instruction, focusing on the use of registers and buses.
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After the instruction LDA 250 has been fetched and decoded, the Execute phase begins:
How it all connects
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Glossary
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Quick check
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Revision flashcards
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What is the Von Neumann architecture?
A computer architecture where program instructions and data are stored in the same memory and share the same data bus for transfer.
Key takeaways
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Instructions and data are stored in the same memory unit.
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Instructions and data use the same bus to travel between the memory and the CPU.
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Instructions are fetched and executed sequentially, one after another.
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This design allows a program to be treated as data, meaning it can be read, modified, and written just like any other data.
Practice — then mark it
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Test Your Knowledge on CPU Architecture
Test Your Knowledge on CPU Architecture
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