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9618 · 15.2

Boolean Algebra and Logic Circuits — common mistakes

Common exam mistakes on 9618 Boolean Algebra and Logic Circuits. Learn what loses marks, then practise the topic with Examiner’s Ink.

Exam tip 1

In exams, always draw your loops clearly on the K-map. When deriving the term for a group, methodically go through each variable (A, B, C, D). If a variable's value is constant within the group (e.g., always 1 or always 0), include it in the term. If it changes, it gets eliminated.

Exam tip 2

Be ready to draw the logic circuit for a half adder and a full adder. For sequential logic, you are expected to understand the function of SR and D-type flip-flops from their truth tables and explain their role in data storage, but you are not typically required to draw their internal gate structure.

Why use a Karnaugh map when I can just use Boolean algebra?

For expressions with 2 or 3 variables, algebra is often just as fast. However, for 4 variables, it becomes very difficult to be certain you have found the absolute simplest form using algebra alone. A K-map provides a systematic, visual method that guarantees the most simplified sum-of-products expression if you follow the rules correctly.

What is the practical difference between a half adder and a full adder?

A half adder can only add two single bits, like the two bits in the least significant column (the 'ones' column) of a binary addition. A full adder can add three bits: two input bits plus a carry-in from the previous column. This makes it possible to chain full adders together to create a multi-bit adder (e.g., an 8-bit adder is made of one half adder and seven full adders).

Why is the S=1, R=1 state in an SR flip-flop considered 'invalid' or 'forbidden'?

In an SR flip-flop made from NOR gates, setting S=1 and R=1 forces both the output Q and its complement Q\overline{Q} to be 0. This violates the fundamental rule that Q and Q\overline{Q} must be opposites. The state is also unstable; if S and R return to 0 simultaneously, the final state of the flip-flop is unpredictable (a 'race condition').

What is the purpose of the clock signal in a D-type flip-flop?

The clock signal provides synchronisation. The D-type flip-flop only pays attention to its data (D) input at a very specific moment—the instant the clock signal transitions from low to high (a rising edge) or high to low (a falling edge). At all other times, the D input can change without affecting the stored output Q. This allows many flip-flops in a larger circuit (like a processor register) to change state simultaneously and in an orderly fashion.