Central Processing Unit (CPU) Architecture — common mistakes

When asked to describe the Fetch-Decode-Execute cycle, be precise. Use the full names of the registers (e.g., 'Program Counter', not just 'PC'). State which bus is being used (address, data, control) and the direction of data flow. A common mistake is mixing up the roles of the MAR and MDR. Remember: MAR holds the address, MDR holds the data.

The key difference is how they handle data and instructions. Von Neumann architecture uses a single, shared memory and bus for both. Harvard architecture uses separate memories and buses for data and instructions. This allows simultaneous fetching, which can be faster, but it's more complex. Modern CPUs often use a hybrid model, with a Von Neumann main memory architecture but separate L1 caches for data and instructions (a Harvard feature).

No, they are very different. A quad-core 3 GHz CPU has four processing units, each running at 3 billion cycles per second. This is excellent for multitasking or running software specifically designed for parallel processing. However, a single task that cannot be split across cores will only run on one core at 3 GHz. A hypothetical 12 GHz single-core CPU would run that same single task four times faster, but would be less efficient at multitasking.

The MAR's job is to specify a location in memory. The CPU only ever sends an address to the memory system; it never needs to read an address from memory. Therefore, the MAR and the address bus are unidirectional. The MDR, however, handles the actual data. It needs to receive data from memory (a read operation) and send data to memory (a write operation), so it must be bidirectional, as must the data bus.