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9618 · 4.1

Central Processing Unit (CPU) Architecture — practice questions

Practice and worked examples for 9618 Central Processing Unit (CPU) Architecture. Short previews only — attempt the full question in MarkScheme against the official scheme.

Worked example 1

An instruction ADD #5 is stored at memory location 102. The Program Counter (PC) currently holds 102 and the Accumulator (ACC) holds the value 12. Describe the steps of the Fetch-Decode-Execute cycle for this instruction, showing the state of the PC, MAR, MDR, CIR, and ACC.

Show solution outline

The instruction means 'add the immediate value 5 to the contents of the Accumulator'.

1. Fetch Phase:

  • The contents of the PC (102) are copied to the MAR. MAR ← [PC]
  • The address 102 is sent along the address bus to main memory. A 'read' signal is sent on the control bus.
  • The instruction at location 102 (ADD #5) is copied from memory to the MDR via the data bus. MDR ← [Memory]
  • The PC is incremented to point to the next instruction. PC ← [PC] + 1, so PC is now 103.

2. Decode Phase:

  • The contents of the MDR (ADD #5) are copied to the CIR. CIR ← [MDR]
  • The Control Unit decodes the instruction in the CIR. It identifies the operation (ADD) and the operand (the immediate value 5).

3. Execute Phase:

  • The operand (5) is sent to the ALU.
  • The contents of the ACC (12) are also sent to the ALU.
  • The ALU performs the addition: 12 + 5.
  • The result (17) is stored back into the Accumulator. ACC ← 17.

The cycle is now complete for this instruction and would begin again by fetching the instruction at address 103.

Worked example 2

An instruction LDA 250 is being executed. This instruction means 'load the data from memory address 250 into the Accumulator'. The data at address 250 is the value 99. Describe the 'Execute' phase of the FDE cycle for this instruction, focusing on the use of registers and buses.

Show solution outline

After the instruction LDA 250 has been fetched and decoded, the Execute phase begins:

1. Address Transfer:

  • The address part of the instruction in the CIR (250) is copied to the MAR. MAR ← 250

2. Memory Read Operation:

  • The address 250 is placed onto the Address Bus.
  • The Control Unit sends a 'memory read' signal along the Control Bus.

3. Data Transfer:

  • Main memory responds by placing the data from location 250 (the value 99) onto the Data Bus.
  • This data travels along the Data Bus and is copied into the MDR. MDR ← 99

4. Load into Accumulator:

  • The contents of the MDR (99) are copied to the Accumulator. ACC ← 99

The execution is now complete. The Accumulator holds the value that was at memory location 250.

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